In the electronic arts it is often desired to perform access to a RAM by at least two data buses of different width in respective modes of operation due to respective applications. Typically, but not necessary, in each mode of operation/application the whole RAM is accessed by only one data bus with a specific bus width. That is, this bus transmits data in units of words of a width equal to its bus width. The RAM itself is organized in words of the storage word width which is equal to the largest bus word width or a multiple thereof. Then the basic data unit in the memory is the largest bus word width. Smaller data units, i.e. from buses of smaller word width, are stored as basic data units where not all data bits are used. In the case that the storage word width is a multiple of the largest bus word width, additionally, multiplexing provides storing multiple of the largest bus word width words within one storage word.
Storing of smaller data words from buses of smaller word width results in incomplete use of the memory space. In an extreme case of one bit words stored in a memory configured in eight bit words, this can leave seven eighths of the memory space unused.
FIG. 1 illustrates a prior art DRAM comprising data storage 10 for storing digital information in bit array cells, row address decoder and driver 12 for addressing a selected row of bit array cells, and sense cells and column drivers 14 for sensing the charge status of bit array cells and driving selected columns of bit array cells. The data transfer to and from data storage 10 is illustrated vertically in the right hand side of FIG. 1 and further drawings. The control signal transfer is illustrated mainly horizontally in the left hand side of the drawings. Data storage 10 is organized by way of example in sixteen rows and sixteen columns of bit array cells, thus storing words of a storage word width of sixteen. Data storage 10 is connected with sense cells and column drivers 14 by internal connections 16 having a width equal to the storage word width of sixteen and also equal to the number of sense cells. Sense cells and column drivers 14 serve as a port for exchanging data with data bus 18 having a width equal to the number of sense cells, e.g. sixteen. Lines for sixteen parallel bits are numbered zero to fifteen [15:0].
Electrical connection of the sense cells and column drivers 14 with data storage 10 or data bus 18 is controlled by write signal wr1 and read signal rd1 on signal lines 20. The four-bit address [3:0] within data storage 10 is submitted together with enable signal en to row address decoder and driver 12 via address bus 22. Upon a valid enable signal, row address decoder and driver 12 selects the addressed one of the sixteen rows of bit array cells by enabling the respective one of row enable lines 24.
FIG. 2 illustrates another prior art DRAM with two extensions compared to that of FIG. 1, whereby similar parts have like but primed reference numbers. The first extension is that data storage 10' is organized by way of example in sixteen rows but thirty-two columns of bit array cells, thus storing words of a storage word width of thirty-two. Thus, two words of width sixteen bits are stored within one thirty-two bit word storage by multiplexing (muxing) by column multiplexer 26 between sixteen bits wide sense cells and column drivers 28 and thirty-two columns of bit array cells of data storage 10'. Only 16 bits of the 32-bit word, are accessed on a read/write operation. All even bits, compose the even address word (addr[0] is driven with `0`), and all the odd bits compose the odd address word (addr[0] is driven with `1`). The address space of data storage 10' is increased by a factor of two as is the data storage 10' itself by the doubled word width. Therefore, another address bit is now provided to a total of five address bits, four of which [4:1] are fed to row address decoder and driver 12' as before and address bit [0] is fed to column decoder 30 via address line 32. Column decoder 30 controls column multiplexer 26 according to the value of address bit [0] via multiplexer lines 34. The main reason for multiplexing is to gain faster address decoding timing (two parallel paths of decoding), in addition to a more efficient layout implementation of the sense cells, that can occupy width of two bit slices of the RAM. By muxing, a much simpler circuit is provided between row address decoder and driver 12' and data storage 10' at the expense of a slightly more complicated circuitry between sense cells and column drivers 28 and data storage 10'.
The second extension is that DMA bus 36 (also of width sixteen) is connected to sense cells and column drivers 28. Sense cells and column drivers 28 is now of multi-port type for serving both busses. Bus selection and access to the selected bus is controlled by write signal wr1 and read signal rd1 on signal lines 20' for data bus 18' and by write signal wr2 and read signal rd2 on signal lines 38 for DMA bus 36.
The advantage of this RAM is that the entire storage space of data storage 10' can be used when storing data of a basic word width smaller than the storage word width.
Nowadays, products using RAM can have different modes of operation, whereby data of different word width has to be stored in the RAM. Data of different word width is exchanged with different data busses. According to the state of the art, the storage word width is chosen to correspond to the basic word width, i.e. equal to or a multiple of the basic word width, defined as the largest bus word width. Smaller bus word widths data are stored within one basic word, leaving bits unused.
Accordingly, there is a need to have a RAM that allows the storage of data having a word width smaller than the basic word width of the storage. This need is met by the devices and methods with the features of the independent claims. Additional features of the dependent claims provide further advantages.